2. Radiation effects in semiconductor devices, circuits and systems

Books

Techniques for radiation effects mitigation in ASICs and FPGAs handbook, ESA, 2015
Review of radiation hardening techniques for Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs), issue by the European Space Agency (ESA).

J. - L. Autran, D. Munteanu – Soft errors: from particles to circuits, CRC Press, 2015.
This book addresses the issues of soft errors in digital circuits exposed to ionizing radiation. All aspects of the design, use, application, performance, and testing of devices, circuits and systems are analyzed.

M. Bagatin, S. Gerardin – Ionizing radiation effects in electronics: from memories to imagers, CRC Press, 2016.
This book provides comprehensive coverage of the effects of ionizing radiation on state-of-the-art semiconductor devices. It also offers valuable insight into modern radiation-hardening techniques for integrated circuits.

M. Nicoladis (Editor) – Soft errors in modern electronic systems, Springer, 2012.
This book is a collection of research results of different authors, illustrating the state-of-the-art achievements and open issues in the field of soft errors.

K. Iniewski (Editor) – Radiation effects in semiconductors, CRC Press, 2011.
This book covers the results of renowned authors in the field of radiation effects, including both TID and SEEs. The aspects of radiation effects in semiconductors are analyzed from the perspective of both terrestrial and space applications.

S. Mukherjee – Architecture design for soft errors. Morgan Kaufman, 2008.
This book provides a comprehensive description of the architectural techniques to address the soft error issues in electronic systems. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them.



Scientific articles

Selected review articles on soft errors in integrated circuits (ICs) and rad-hard IC design:

P. E. Dodd, L. W. Massengill, “Basic mechanisms and modeling of single event upset in digital microelectronics”, IEEE Trans. Nucl. Sci, Vol. 50, No. 3, 2003
Physical mechanisms responsible for nondestructive single-event effects in digital micro-electronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

D. Munteanu, J.-L. Autran, L. W. Massengill, P. Gouker, “Modeling and simulation of single-event effects in digital devices and ICs”, IEEE Trans. Nucl. Sci, Vol. 55, No. 4, 2008.
This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs).

V. Ferlet-Cavrois, L. W. Massengill, P. Gouker, “Single event transients in digital CMOS - review”, IEEE Trans. Nucl. Sci, Vol. 60, No. 3, 2013.
The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore’s Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.

R. Baumann, “Soft errors in advanced computer systems”, IEEE Design and Test of Computers, 2005.
This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent. The discussion covers ground-level radiation mechanisms that have the most serious impact on circuit operation, along with the effect of technology scaling on soft-error rates in memory and logic.


Selected IHP’s journal articles on soft errors and rad-hard design:

F. Kuentzer, M. Krstic, Soft error detection and correction architecture for asynchronous bundled data designs, IEEE Transactions on Circuits and Systems: Regular Papers, 2020.
In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style.

Y. Li, A. Breitenreiter M. Andjelkovic, J. Chen, M. Babic, M. Krstic, Double cells upsets mitigation through triple modular redundancy, Microelectronics Journal, Vol. 96, 2020.
A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.

J. Chen, T. Lange, M. Andjelkovic, A. Simevski, M. Krstic, Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning, Microelectronics Reliability, 2020.
This work introduces an embedded approach for the prediction of Solar Particle Events (SPEs) in space applications by combining the real-time Soft Error Rate (SER) measurement with SRAM-based detector and the offline trained machine learning model. The proposed approach is intended for the self-adaptive fault-tolerant multiprocessing systems employed in space applications. With respect to the state-of-the-art, our solution allows for predicting the SER one hour in advance and fine-grained hourly tracking of SER variations during SPEs as well as under normal conditions.

M. Andjelkovic, M. Krstic, R. Kraemer, Study of the operation and SET robustness of a CMOS pulse stretching circuit, Microelectronics Reliability, Vol. 82, 2018.
This paper analyzes the normal response and the sensitivity to Single Event Transients (SETs) of a CMOS pulse stretching circuit used for the SET pulse width measurement. The pulse stretcher based on two cascaded asymmetrically sized inverters, designed in IHP's 130 and 250 nm bulk CMOS technologies, has been studied.

M. Krstic, S. Weidling, V. Petrovic, E. Sogomonyan, Enhanced architectures for soft error detection and correction in combinational and sequential circuits, Microelectronics Reliability, Vol.56, 2016.
In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops.

V. Petrovic, G. Schoof, Z. Stamenkovic, Fault-tolerant TMR and DMR circuits with latchup protection switches, Microelectronics Reliability, Vol. 54, 2014.
The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor.


Selected IHP’s conference articles on soft errors and rad-hard design:

F. Kuentzer, M. Herrera, O. Schrape, P. Beerel, M. Krstic, Radiation hardened click controllers for soft error resilient asynchronous architectures, in Proc. 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2020.
In this paper a generalized method for hardening asynchronous Click-based controllers is introduced, where a combination of spatial redundancy and Guard Gate (GG) is used to mitigate Single Event Transients (SET) and Single Event Upsets (SEUs). Two Click controllers that can benefit from the RHBD methodology are presented, each one targeting a recently proposed soft error resilient asynchronous architecture, the Soft Error Resilient Asynchronous Design (SERAD) and the Asynchronous Full Error Detection and Correction (AFEDC).

M. Andjelkovic, J. Chen, A. Simevski, O. Schrape, M. Krstic, R. Kraemer, Monitoring of particle flux and LET variations with pulse stretching inverters, in Proc. European Conference on Radiation Effects on Components and Systems (RADECS), 2020.
This work investigates the use of pulse stretching inverters for monitoring the variation of particle flux and LET in terms of the SET count rate and SET pulse width, respectively. The proposed solution can be used to dynamically trigger the fault tolerance mechanisms within a self-adaptive system. Analysis was done with SPICE simulations for 130 nm CMOS technology.

A. Simevski, O. Schrape, C. Benito, M. Krstic, M, Andjelkovic, PISA: Power-robust microprocessor design for space applications, in Proc. IEEE International Online Testing Symposium (IOLTS), 2020.
Following the same line of motivation we introduce the PISA multiprocessor chip with improved power robustness for space applications which is successfully produced and tested in IHP 130 nm technology. The paper brings several novelties in respect to the current state-of-the-art. The chip uses the Waterbear framework in which the multiprocessor cores can be dynamically put in one of three different operating modes according to the current application requirements regarding performance, power consumption and fault tolerance.

A. Simevski, P. Skoncej, C. Calligaro, M. Krstic, Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications, Proc. 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019.
Space applications constantly require integration of more processing capabilities and greater memory capacity, at reduced weight and power consumption. The IHP 130 nm technology is a commercially-qualified and radiation-assessed technology which is sufficiently aggressive for the conservative approach in the space area. In this process node we realize a radhard 16 Mbit Multi-Chip Module (MCM) SRAM with improved characteristics in comparison to competitor SRAMs. Moreover, the real novelty is the scalable master-slave architecture of the System-in-Package (SiP) with Error Detection and Correction (EDAC), and scrubbing mechanisms which are now at the SiP level.



Presentations

Z. Stamenkovic, V. Petrovic, A Comprehensive Approach to Fault Tolerance: Device, Circuit, and System Techniques, 17th IEEE Latin-American Test Symposium (LATS), 2016.
This work presents a design methodology for fault-tolerant ASIC that is based on radiation-hard technology, redundant circuits with latchup protection, additional implementation steps during logic synthesis and layout generation, and power gating. Enhancements have been made within the standard ASIC design flow in order to incorporate redundancy and power-switch cells and, consequently, enable protection against single-event upset (SEU), single-event transient (SET), and single-event latchup (SEL).

S. Gerardin, Ionizing Radiation Effects on Advanced CMOS Technologies, 2009.
This work reviews the basic physical mechanisms and effects of ionizing radiation on electronic devices and circuits.

D. Loveless, Hardening-by-Design Techniques for Analog and Mixed-Signal ASICs, SERESSA, 2015.
This presentation reviews the device-, circuit- and system-level techniques for improving the radiation hardness of integrated circuits.

S. Buchner and D. McMorrow, Overview of Single Event Effects, SERESSA, 2015.
This presentation reviews the basics of Single Event Effects and is a very useful guide for beginners in this field.



Theses

H. Xie, Study of Single Event Transient Error Mitigation, 2017.

G. Kazma, Analysis of Single Event Upsets Propagation at Register Transfer Level in Combinational and Sequential Circuits Based on Satisfiability Modulo Theories, 2017.

N. Mahatme, Design Techniques for Power-Aware Combinational Logic SER Mitigation, 2014.

M. Ebrahimi, Cross-layer Soft Error Analysis and Mitigation at Nanoscale Technologies, 2016.

R. Harrington, Models for Characterizing Single-Event Effects in Advanced Technology Circuits, 2019.

A. Zimpeck, Circuit-Level Approaches to Mitigate the Process Variability and Soft Errors in FinFET Logic Cells, 2019.